New 
Senior IP RTL Design Engineer
 Microsoft | |
 United States, Oregon, Hillsboro | |
 Nov 28, 2024 | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior IP RTL Design Engineer to help achieve that mission.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Computer Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior IP RTL Design Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
ResponsibilitiesOwn subsystem integrating several industry standard IPs.Specifying and micro-architecting digital blocks, and performing concept studies to guide performance, power, and gate count.Write Register Transfer Level(RTL) code for blocks based on architectural specifications.Participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team.Assess and then refine the implementation for area, power, and performance.Define, create, and maintain project documentation, including design documents with analysis reports.Collaborate with architecture, subsystem owners, and IP providers to configure the IP to maximize performance for various use cases.Grow your micro-architectural knowledge of your own blocks as well as other blocks in the System on Chip(SoC).Describe the power intent of the design through Unified Power Format(UPF).Perform design quality checks such as Lint, Clock Domain Crossing(CDC), Reset Domain Crossing(RDC), Low Power Intent, Synthesis, Logic Equivalence.Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.Automate tasks using scripting for efficiency.Delight your customers who receive your deliverable by providing high quality functional block on schedule and with professional integrity.Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.Challenge the status quo with a growth mindset.OtherEmbody our Culture and Values | |