Principal Physical Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

In this role, you will:

• Lead Chip-Level Physical Design: Oversee all aspects of chip-level Place and Route (PNR) activities, including floor planning, power grid design, clock tree synthesis, routing, and timing closure.
• Perform Detailed Analysis: Conduct comprehensive timing, power, and signal integrity signoff, ensuring designs meet stringent performance and reliability standards.
• Manage Physical Verification: Handle physical verification tasks such as DRC, LVS, and antenna checks to comply with advanced semiconductor process requirements.
• Collaborate Across Teams: Work closely with frontend, integration, and verification teams to ensure cohesive design implementation and successful project tapeouts.
• Develop Methodologies: Contribute to the development and refinement of physical design methodologies and flows, enhancing design efficiency and project alignment.
• Mentor and Lead: Provide technical guidance and mentorship to junior engineers, fostering a collaborative and innovative team environment.

What We're Looking For

• Educational Background: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs.
• Technical Proficiency: Expertise in hierarchical design strategies, deep sub-micron technologies (e.g., 7nm, 5nm), and familiarity with industry-standard physical design tools such as Cadence Innovus and Synopsys IC Compiler.
• Analytical Skills: Strong capabilities in timing analysis (e.g., Tempus, PrimeTime) and EM/IR-Drop/crosstalk analysis tools (e.g., Voltus, Celtic, PTSI).
• Programming Skills: Proficiency in scripting languages (Makefile, Tcl, Perl) to automate and enhance design workflows.
• Leadership Qualities: Detail-oriented, self-motivated, and effective communicator with a collaborative approach to team projects.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.