SoC Static Timing Analysis (STA) Lead

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THE ROLE:

We are looking for an experienced SoC Static Timing Analysis (STA) Lead who has a strong background or a keen interest in Physical Design Implementation. You have a proven track record of successfully managing high-performance and complex SoC designs. You pay close attention to Power, Performance, and Area while overseeing schedules and controlling costs. In this senior position, you will be challenged as you lead timing closure for next-generation products at advanced nodes with our top-tier SoC engineering team

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Develop and establish timing closure methodologies and strategies for SoC and IP blocks to ensure compliance with requirements, and provide technical guidance to execution teams.
• Oversee STA closure for complex SoC designs featuring chiplet and 3D stack interfaces.
• Leverage extensive knowledge and experience in physical design and full-chip timing to tackle large, cutting-edge designs, ensuring high-quality, on-time delivery.
• Understand the SoC as an integrated system while optimizing for performance and power.
• Collaborate cross-functionally with IP, Domain, CAD, and Methodology teams to identify and address intricate technical challenges and risks, and create solutions to meet product specifications.
• Share knowledge and contribute to various SoC functions.
• As the overall STA lead, take responsibility for architectural analysis and the scoping/assessment of feature changes.
• Partner closely with design teams to refine area and floorplan, set timing targets, and secure performance sign-offs.
• Assist Post-Silicon teams with debugging and resolving timing issues.

PREFERRED EXPERIENCE:

• Strong foundation in SoC Physical Design implementation, with expertise in one or more areas such as STA closure, methodology, margining, binning, PVT corners, clocks, and resets.
• Extensive experience in ASIC Physical Design at the latest process nodes.
• Experience with timing closure and sign-off for 3D stack/chiplet designs is a plus.
• Proficient in using CAD tools from Synopsys, Cadence, and Mentor Graphics.
• Exceptional communication, management, and presentation skills.
• Skilled in collaborating with prominent thinkers and senior SoC leaders, demonstrating strong interpersonal abilities to work effectively with teams across various locations.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in related discipline preferred

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.