Lead Design Verification Engineer

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At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives.
THE PERSON:

We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC.

• Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality.

• Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features.

• Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables.

• Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip.

• Develop and maintain automation and regression infrastructure, including CI/CD integration.

• Drive coverage closure and signoff for IP and SoC-level verification.

• Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization.

• Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

PREFERRED EXPERIENCE:

• Proven line management experience, including hiring, mentoring, and performance management of DV engineers.

• Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects.

• Experience with chip-level verification for networking ASICs, switches, or routers.

• Familiarity with traffic generators, packet-level verification, and network protocol stacks.

• Knowledge of SystemC, C testbenches, or hardware/software co-verification.

• Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce).

• Prior experience leading cross-site or multi-IP verification efforts.

• Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in related discipline preferred

LOCATION:

Santa Clara, CA

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.