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Principal Engineer, Physical Design

Marvell Semiconductor, Inc.
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Mar 13, 2026

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

Responsible for the physical implementation of complex integrated circuits (ICs). Responsible for Power Integrity analysis and signoff for Static/Dynamic IR and EM at the SoC level for Advanced process nodes. Work with a variety of other disciplines and leaders in Physical Design, Integration, and Timing. Define SoC power targets with the technical lead, including coordination with package team. Manage and work with tool vendors on any related issues of the tool or bring-up of the tool on a design. Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes. Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation. Responsible for managing tool and flow settings to ensure the team is setup for success during analysis. Perform complex block Synthesis, floorplan, PnR, Timing Closure, Physical Closure. Wage $193,000.00 - $223,000.00 per year.

What We're Looking For

Bachelor's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include five (5) years with each of the following:

* Power Signal Integrity (SoC level EMIR) and Closure on multiple ASICs/SOCs, at a block and sub-system (partition) level.
* Correlating Early Rail Analysis in PD tools, with results from Signoff.
* Power Integrity Signoff methodology and flow development.
* Running, debugging, and providing solutions for Static and Dynamic IR and EM at all levels of SoC hierarchy.
* Both vector-less and vector modes of analysis at different phases of the SoC development.
* Low power concepts and UPF, such as power gating and shutoff as it relates to power delivery and analysis.
* Circuit, Physical Design and Timing.
* TCL and Python languages.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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