R&D Engineering, Staff Engineer (Fusion Compiler GPU Acceleration)

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

• Collaborate closely with foundries, research institutions, and ecosystem partners on advanced-node technology development and DTCO initiatives.
• Evaluate emerging process technologies and assess their PPA potential through comprehensive design studies and analysis.
• Provide design-centric feedback on process technology collaterals, design rules, device architectures, and design enablement methodologies to improve PPA and technology competitiveness.
• Drive Design Technology Co-Optimization (DTCO) activities across process, standard cell, and implementation domains.
• Study and optimize standard cell architectures, libraries, and design methodologies for advanced process technologies.
• Analyze the impact of technology innovations on timing, power, area, routability, yield, and manufacturability.
• Work with Synopsys R&D teams to enhance implementation flows, develop new product capabilities, and improve EDA engines for next-generation nodes.
• Identify technology limitations, design challenges, and optimization opportunities, and drive solutions through close collaboration with internal and external partners.
• Develop benchmarks, methodologies, and best practices for evaluating future technology nodes and design enablement strategies.

• Drive industry-leading PPA optimization for advanced technology nodes.
• Enable successful deployment and adoption of next-generation semiconductor technologies.
• Influence foundry technology development through design-driven analysis and actionable feedback.
• Advance DTCO methodologies that improve technology scalability, manufacturability, and product competitiveness.
• Enhance Synopsys EDA tools and flows to support future process technologies.
• Enable optimized standard cell architectures and design methodologies for improved design productivity and silicon efficiency.
• Help shape the future of semiconductor innovation through collaboration with leading foundries and research organizations.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10+ years of industry experience in physical implementation, design enablement, technology development, or DTCO for advanced semiconductor technologies.
• Strong understanding of advanced process technologies (4nm and below preferred).
• Hands-on experience in physical design and implementation methodologies, including place-and-route, timing closure, power optimization, and PPA analysis.
• Demonstrated experience in Power, Performance, and Area (PPA) optimization across advanced technology nodes, with a deep understanding of the design and technology tradeoffs impacting silicon efficiency.
• Strong knowledge of Design Technology Co-Optimization (DTCO) methodologies and the interaction between process technology, standard cell architecture, and design implementation.
• Experience in standard cell design, library architecture, characterization, and optimization, including evaluation of cell-level PPA tradeoffs and scalability for advanced nodes.
• Experience collaborating with foundries on technology development, process enablement, DTCO, or advanced-node qualification activities.
• Strong understanding of IC design and implementation methodologies, including floorplanning, placement, clocking, routing, timing closure, and design rule optimization.
• Strong analytical and problem-solving skills with the ability to evaluate emerging technologies and identify optimization opportunities.
• Excellent communication and collaboration skills.

• Collaborative and highly effective in cross-functional environments.
• Passionate about innovation and continuous learning.
• Detail-oriented with strong analytical thinking.
• Proactive in identifying challenges and driving solutions.
• Comfortable navigating complex technical problems across design, process, and EDA domains.
• Strong communicator capable of influencing both technical and business stakeholders.

You will be part of a highly skilled team focused on advanced-node technology enablement, DTCO, and PPA optimization. The team works closely with leading foundries, research organizations, and Synopsys R&D groups to evaluate emerging semiconductor technologies, optimize standard cell and design methodologies, and enhance EDA solutions that drive the next generation of silicon innovation.

We offer comprehensive health, wellness, and financial benefits. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.