Senior Silicon Engineer PD CAD Signoff
 Microsoft | |
 United States, California, Mountain View | |
 Nov 27, 2024 | |
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OverviewThe Azure Hardware Systems and Infrastructure team at Microsoft is spearheading the technology revolution, leading the creation and implementation of innovative cloud infrastructure solutions. Within our Silicon Engineering division, you will get the chance to collaborate with some of the industry's brightest minds, contributing to the future of Artificial Intelligence and Computing. We are looking for aSenior Silicon Engineerto join our team! If you are like tackling complex Register Transfer Logic (RTL) /Implementation challenges and have a keen interest in driving the associated methodology for large and intricate digital System on Chip (SoC), this is the perfect place for you! You will be part of a team that is responsible for developing and delivering the latest Electronic Design Automation (EDA) technologies to various silicon teams within Microsoft. In this role, you will be tasked with defining, implementing, and delivering logical equivalence checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites within the Microsoft silicon engineering organization.
ResponsibilitiesEstablish Logical Equivalence Checking (LEC)/Formal Equivalence Verification (FEV) methodology for hierarchical and block-level partitions between RTL, Design for Testability (DFT)-inserted RTL and Gate-level/Power-Ground (PG) Connected netlists on Microsoft's next-generation large and complex SoCs.Enhance design productivity with advanced scripting skills for development/maintenance of large CAD (Computer Aided Design) flow systemsPerform detailed debug/analysis to guide the RTL and physical design teams across Microsoft's silicon portfolio in addressing and solving challenging logical equivalence failures.Perform cross-functional decision making across UPF (Unified Power Format)/Low Power methodology/architecture, DFT methodology, Synthesis, Place and Route and Extracted Timing model generation in Timing Analysis tools to embellish Logical Equivalence modelling.Contribute to raising the standard by discovering innovative synthesis/optimization strategies for optimal power, performance, area and yield without overloading the Logical Equivalence Solver algorithms.Implement automatic Functional Engineering Change Order (ECO) methods pre-/post-mask to generate faster, well-optimized, and functionally equivalent patch files.Collaborate closely with the EDA partners to identify and deliver the best and most advanced solutions for effective Logical Equivalence closure while optimizing runtimes.Embody our Culture and Values | |